Output buffers are integrated circuits ("ICs") used to interface a digital input signal to a typically large capacitive and/or resistive load that is often a system buss or an interconnect cable. Many output buffers include an enabling function whereby the buffer input signal appears as the buffer output only when an enabling signal is present.
FIG. 1A depicts generically such an output buffer 2, which typically operates from an upper power supply Vdd and a lower power supply Vss that is often ground. The buffer receives DATA IN as an input and outputs a DATA OUTPUT signal, providing the OUTPUT ENABLE signal is present (e.g., is a digital "1"). Depending upon the circuit design, DATA OUTPUT may replicate or be an inverted version of DATA IN, and the buffer may enable with the OUTPUT ENABLE is a digital "0". The output of buffer 2 is shown coupled to a load impedance Z.sub.L that may be represented generally by a resistance R.sub.L shunted by an effective capacitive load C.sub.L. Load impedance Z.sub.L typically represents a long buss, or perhaps a signal cable of many meters lengths. In some applications, Z.sub.L may be primarily a load resistance e.g., R.sub.L, or a load capacitance C.sub.L, or a combination of each.
As shown in FIG. 1A, buffer 2 may be implemented with bipolar transistors, complementary metal-on-semiconductor ("CMOS") transistors, or a combination of each ("Bi-CMOS"). Buffer 2 typically will include two inverters I1 (here a NAND gate) and I2 coupled in series, or I3 (here a NOR gate) and I2 coupled in series. The output of the first inverter is presented as input to the second inverter, and the output of the second inverter is the buffer output, which has the same phase as the input to the first inverter. In the CMOS implementation of FIG. 1A, each inverter comprises a P-type pull-up metal-on-semiconductor ("PMOS") transistor and an N-type MOS ("NMOS") transistor coupled in series between Vdd and Vss. For example, I1 may comprise a PMOS transistor P1 (not shown) and an NMOS transistor N1 (not shown), I2 comprises PMOS transistor P2 and NMOS transistor N2, and I3 comprises transistors P3, N3 (not shown). Because I2 drives load Z.sub.L, output transistors P2 and N2 will generally be larger sized devices than the transistors comprising I1 or I3.
The enabling function may be implemented using the NAND gate (I1), INVERTER and NOR gate (I3) logic shown, or using other techniques well known to those skilled in the relevant art.
When DATA IN is a digital "1", within I1, P1 turns off and N1 turns on, and the first inverter output is a digital "0". Upon receipt of this "0", in the second inverter I2, P2 turns on, N2 turns off, and the DATA OUTPUT will be a digital "1", and buffer 2 sources current into Z.sub.L. When DATA IN is a digital "0", P1 turns on, N1 turns off, and the output from the first inverter is a "1". Upon receipt of this "1", P2 in the second inverter turns off, N2 turns on, DATA OUTPUT is a "0", and buffer 2 sinks current from Z.sub.L.
FIG. 1B depicts voltage and current waveforms associated with output buffer 2. For example, although DATA IN is "1" before time t.sub.0, it is only after the OUTPUT ENABLE signal goes high that buffer 2 is enabled to provide the DATA OUTPUT signal. At time t.sub.1, DATA IN goes low and, since OUTPUT ENABLE is still enabling buffer 2, the DATA OUTPUT signal also goes low. In the DATA OUT waveform, the voltage waveform drawn in phantom represents the case of a relatively large load capacitance C.sub.L. When C.sub.L is not especially large, the output voltage waveform slews more rapidly, but can ovrshoot and undershoot as shown.
It is thus appreciated from the DATA OUT waveform that as C.sub.L increases, the output voltage slew rate (dV/dt) decreases. To compensate for this, it is necessary to implement buffer 2 with larger output inverter transistors, e.g., transistors that can source or sink more current (i). (Of course, this assumes that the IC containing buffer 2 has sufficient area whereon to fabricate larger transistors.) The ability to compensate for a large C.sub.L by increasing output buffer current follows from the equation: EQU i=C.sub.L dV/dt
Although large current handling transistors can improve output voltage slewrate, a large current capability can be detrimental. In practice, buffer 2 will not function perfectly because the various pull-up and pull-down transistors do not change states in perfect synchronism. The output buffer current waveform depicts the total current i.sub.o flowing through buffer 2. The i.sub.o current wave form drawn in phantom represents total current drawn by the buffer when the various buffer transistors are themselves large devices, e.g., devices with a relatively large drain current.
Note from this waveform that current spikes occur when the buffer transistors change states, for example at times To and t.sub.1. These spikes are created because for a brief moment, the PMOS and NMOS transistors in each inverter are simultaneously on, thus presenting a low impedance current path between the Vdd and Vss power supplies. In addition, current spiking occurs because the load capacitance C.sub.L component of Z.sub.L is being charged toward Vdd or discharged toward Vss (depending upon the direction of the output state change).
Thus, the i.sub.o waveform in FIG. 1B suggests that compensating for a large load capacitance C.sub.L by implementing buffer 2 with large current transistors will aggravate current spiking. Those skilled in the art will appreciate that the current spiking waveforms can contain many high frequency components that represent electromagnetic ("EM") and radio frequency ("RF") noise that can interfere with other signals implemented on the IC containing buffer 2, and with signals elsewhere in a system contain this IC.
The current spiking can also contribute to crosstalk between various signal lines on a system including the output buffer, and can also contribute to unwanted transmission line reflections. Further, current spiking represents transient bursts of heat that must be safely dissipated by the transistors within buffer 2.
If C.sub.L were reliably known, an output buffer comprising suitably sized transistors might be readily designed and implemented. However, in so doing, existing standard buffer circuit fabrication may have to be substantially revised, especially where significantly greater output current must now be sourced/sinked. Similarly, in some applications if the magnitude of R.sub.L were known, the output buffer could be suitable designed. For example, in an application wherein DC current flow occurs, knowledge of the magnitude of R.sub.L would permit sizing the output transistors within the buffer.
Further, in some system applications, the magnitude of C.sub.L and/or R.sub.L may not be known a priori. For example, in FIG. 2A, the host computer 4 in a computer system may be coupled to one, two or N hard disc drive units 6, wherein the host computer-disc drive interface includes an output buffer 2, such as depicted in FIG. 1A.
In FIG. 2A, if the output buffer were designed to source/sink current representing N hard disc drive loads, the output buffer will source/sink excessive current when fewer than N loads are coupled to the host computer. When driving less than N loads, the excessive current would improve the output voltage slew rate, but would also increase the magnitude of the current spikes during transition, as well as the transient heat required to be dissipated by the buffer transistors. On the other hand, if the output buffer were designed to source/sink current representing four loads, then the buffer voltage slewrate would be impermissibly slow if more than four loads were to be driven. See, for example, the DATA OUT phantom waveform shown in FIG. 1B depicting a slow voltage slewrate.
FIG. 2B depicts another system application wherein a hard disc drive unit 6 may be required to provide data to one or more host computers 4 that are coupled to the disc drive output buffer 2 through different lengths of cable. The result is that the output buffer 2 may be coupled to a nominal effective load capacitance C.sub.L, or to a substantially different magnitude load capacitance, depending perhaps on the length of cable separating the host from the buffer. Optimizing the output buffer to drive a nominal value C.sub.L may represent a poor design choice when driving a substantially different capacitive load.
While FIGS. 2A and 2B demonstrate the problem of providing a suitably designed output buffer between one or more host computers and one or more hard disc drive units, the problem can exist in other environments as well.
Thus, there is a need for a generic output buffer that may be implemented using existing fabrication designs, and whose output source/sink current may be readily modified according to the capacitive load to be driven. To help reduce system noise, such output buffer preferably should include a mechanism for reducing noise spikes.
The present invention discloses such an output buffer.